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Transmeta turns to Fujitsu for 90nm Efficeons

Blow to TSMC

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Transmeta has chosen Fujitsu to fab the 90nm version of its as-yet-unshipped 130nm Efficeon processor.

Efficeon - aka the TM8000, and previously known by its codename, 'Apollo' - is due to ship during Q4 this year. The 90nm version is scheduled for a H2 2004 volume release, Transmeta said.

The news is something of a blow for Transmeta's current fab partner, TSMC, which has the contract for the 130nm Efficeon.

"Earlier this year we conducted a worldwide investigation and found that Fujitsu's 90nm process delivered the best performance of any technology we evaluated," said Transmeta's president and CEO, Matthew Perry, in a statement.

What particularly tickled Transmeta was the performance of Fujitsu's 40nm gate-length transistors - described by Transmeta CTO Dave Ditzel as delivering "some of the best performance we've seen in the industry".

Work porting Transmeta's Efficeon die design over to Fujitsu's CS100 90nm CMOS process has already begun. CS100 uses 11 metal interconnect layers. Fab work is handled by Fujitsu's Akiruno Technology Center near Tokyo, and it's here that 90nm Efficeons will be produced.

The new chip features upgrades to Transmeta's LongRun power-saving technology and its Code Morphing x86 compatibility software, but that's only to be expected. More interesting is a revised architecture allows the Efficeon to execute up to eight instructions per clock, like IBM's upcoming PowerPC 970. It sports a 256-bit VLIW engine.

The Efficeon will sport three on-chip bus controllers: AGP, DDR 400 and HyperTransport. The latter is clocked at 400MHz. The AGP bus operates at 4x speed. Essentially, then, it integrates its North Bridge onto the die.

The new chip will run everyday applications around 50 per cent faster per clock cycle than the current generation of Crusoe TM5800 can. Multimedia apps will run up to 80 per cent per clock cycle faster, the company claimed. Clock speeds for the part have yet to be announced. ®

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