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IBM boffins boost chip performance by 65%

New techniques improve old processes

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IBM scientists today claimed they have merged two key manufacturing techniques - strained silicon and silicon-on-insulator (SOI)- allowing them to create chips that deliver the performance improvements provided by the former without the implementation headaches the technology has so far caused.

The company also said it had developed a technique it claims will deliver a 40-65 per cent performance improvement for standard CMOS chips. It expects both approaches to be implemented commercially in just a few years' time.

The strained silicon technique - currently being used by Intel to make its upcoming 90nm processors, Prescott and Dothan - improves the electrical efficiency of on-chip circuits by stretching a layer of silicon over a layer of silicon germanium (SiGe). The top layer's silicon atoms align themselves with those in the SiGe layer's wider-spaced crystal lattice, stretching them apart. This improves the flow of electrons through the 'strained' silicon layer.

That, in turn, yields a 20-30 per cent improvement in circuit performance, said IBM, but adding the SiGe layer means the circuits are harder to make and tricky to integrate into existing fabrication processes. That's probably why Intel waited until moving to 90nm before implementing the technique.

To avoid the implementation issues, IBM tried using its established SOI technology in place of SiGe. IBM uses an SiGe layer to strain the silicon lattice, but removes it before fabrication, after applying the strained silicon onto the insulator. The upshot: it gains benefits of strained silicon using what is essentially its standard SOI process. By removing the SiGe layer, it doesn't have to integrate that material into the chip fabrication process per se. It calls the new technique, Strained Silicon Directly on Insulator (SSDOI).

IBM said it had confirmed that removing the SiGe layer leaves the silicon strained by measuring the electron mobility enhancement through a specially constructed sub-60nm field effect transistor (FET) fabricated using SSDOI.

While SSDOI improves the mobility of electrons through a device, the second process, dubbed Hybrid Orientation Technique (HOT), improves the mobility of positive charges, or 'holes', in the other direction.

HOT more than doubles hole mobility by combining two substrates on the same wafer, each with different surface orientations, essentially allowing it to combine the benefits of the two key CMOS FET types, positive and negative. The upshot, says IBM, is a 40-65 per cent performance improvement on a 90nm CMOS device.

Like SSDOI, HOT is "relatively simple" to implement using standard wafer processing techniques, IBM Research's VP for science and technology, Dr. T C Chen, in a statement. "Implementing either could provide the industry with higher performing and lower power chips; combining the techniques could generate even higher performance and lower power."

IBM will detail both techniques at the International Electron Devices Meeting, to be held in Washington DC early next December. ®

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