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TI dribbles out UltraSPARC IV details

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Texas Instruments has disclosed fresh details on the upcoming UltraSPARC IV chip it's building for Sun Microsystems, showing a processor with added kick and low power consumption.

The UltraSPARC IV will be Sun's first mainstream dual-core processor, combining two UltraSPARC IIIs on one piece of silicon. Sun plans to roll out the processor in early 2004 at 1.2GHz and run it up to 2.0GHz over time.

The new chip will have 66 million transistors along with 7.2Mbits of SRAM. The gate length will come in at 65nm, and the chip will consume 90 watts at 1.35 volts.

It's rather difficult to gauge how well the UltraSPARC IV may perform. Sun is saying it will be twice the chip of current 1.0GHz UltraSPARC IIIi processors.

To help gain some perspective, a comparison between the UltraSPARC IV and Sun's other 2004 dual-core chip - Gemini - is helpful. Sun has Gemini, built on two UltraSPARC II cores, coming in at 3x the UltraSPARC IIIi's performance.

Ace's Hardware has done a nice job of stacking Gemini up against AMD's Opteron and Intel's Xeon processors.

A two processor Gemini system holds its own against Xeon processors with much higher frequencies on the SPECint and SPECfp benchmarks. To some degree, this backs up Sun's claim that throwing low-power multicore chips at certain software loads will eventually beat out a single, all powerful chip. As usual though, AMD's Opteron turns this logic on its head. AMD's chip screams on both benchmarks, beating out Intel and Sun by a country mile in most tests.

You can try and match UltraSPARC IV with Gemini, but the two chips are designed for different types of workloads. The UltraSPARC IV will go in Sun's classic enterprise software handling SMP systems, while Gemini will make its way into Web serving blades.

Ace's Hardware also takes a look at where Sun could make some adjustments to the UltraSPARC IV to boost performance based on the design TI showed at the recent Hot Chips conference.

"A rough measurement of the L2 tags on the UltraSPARC IV die photo above suggests they are far larger than the L2 tags on the UltraSPARC III - probably by a factor of eight. The L2 tags store a record of what data in main memory is being cached, so increasing the L2 tags by eight times could allow the L2 size to be increased by a similar degree. Alternatively, the cache line size could be decreased instead, which would increase the cache hit rate.

"A 64 MB L2 cache would likely prove beneficial to large servers running business applications, whereas bandwidth-constrained HPC applications would be less likely to see a significant improvement. 64 MB of SRAM would also be quite expensive, but then again, a 356 mm core is already expensive."

Sun needs to show strong performance with the UltraSPARC IV, as it faces increasing pressure from IBM's well-regarded Power4 chip and its Power5 successor. Itanium 2 has also flexed its muscle in benchmarks, but the slow adoption rates of the processor make it less of an immediate threat.

Sun and IBM do fit into the classic systems company camp in that they try to strike a balance between overall processor performance and trade-offs that must be made to construct a solid server. With Itanic, Intel likes to trumpet its all out speed while ignoring the 130 watts of power and size of the beast.

Sun has some serious work to do when UltraSPARC IV servers start rolling out. It will need to combat IBM's better chip performance while tempering Intel's Itanium marketing blitz.

The company has a loyal customers base, but Sun will have to prove to analysts that its processor roadmap instills enough confidence to attract new business. ®

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