Intel colours in server roadmaps

Codenames galore

IDF Mike Fister, 'the Godfather of Itanium' (yes, really), and head of Intel's Enterprise Platforms Group, coloured in some server CPU and chipset roadmaps at IDF yesterday.

First up the Itanium 2: The Deerfield low-voltage Itanium 2 - it's half the power of Madison - will make its public debut in 2H' 03. Chipzilla is touting Deerfield a tad downmarket - into blades and the like, but no prices yet. Next up is a new mobo, the Tiger 2, which uses Madison and the E8870 chipset - the same as for the other members of the Itanium 2 family. We'd like to give you a shipping date, but if Fister, supplied one, we missed it. Sorry. (Update: Intel has kindly supplied us with a date-ish. Tiger 2 should ship at or near to Madison this summer).

Next up the Xeons. A uniprocessor Xeon 3GHz with a whopping 1MB cache will ship in Q3. In 2004, the first 90nm Xeon, codenamed Nocona, should make its debut. On the multiprocessor front, Fister promised a "greater than 2GHz" flavour with 1MB cache version this year. The first 90nm MP Xeon, codenamed Potomac will be out next year. In due course the Xeon MPs will incorporate up to 4MB cache.

Accompanying the new Xeons are a couple of new chipsets, pencilled for 2004. Lindenhurst is designed for 2-way Nocona, while Twin Castle is a chipset for 4 way Potomacs. All the buzzword standards, including Serial ATA, PCI Epxress and DDR-2 memory, are supported. ®

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