HP plans dual Montecito Intel Itaniums for H1 2003

Twin CPU package to double server processor count

ComputerWire: IT Industry Intelligence

While Intel Corp does not plan to get dual-core 64-bit Itanium processors into the field until sometime in the middle of this decade, Hewlett Packard Co, which has staked its future on the Itaniums, can't sit around and wait for Intel while its competitors all deliver or ready their own dual-core processors for enterprise servers,

writes Timothy Prickett-Morgan.

That's why HP, as we reported months ago, will deliver a dual-core PA-8800 next year. But what we learned last week, as HP was holding its annual conference with industry analysts, was that HP has figured out a way to package two Itanium chips together in a single package so they can plug into one slot.

It's not two cores on a single chip, but two processors side-by-side, sharing one slot and a single L2 cache memory. This will allow HP to double the SMP scalability of its servers without having to significantly re-engineer its server platforms, something the company is wise to do.

IBM was the first to market with a dual-core processor, with the 1.1GHz and 1.3GHz Power4 chips that made their debut in the pSeries 690 server in October 2001. That chip includes two full Power4 cores, a shared 1.5MB L1/L2 cache, and the interconnection electronics to create an eight-way SMP module from four Power4 chips, all packaged on a single multichip module. Both Sun and HP are known to be working on dual-core chips in their respective UltraSparc and PA-RISC processors.

Back in September, David Yen, executive vice president for Sun's Processor and Network Products group, said that the company would deliver a dual-core UltraSparc-IV processor for launch sometime in 2003. This dual-core UltraSparc chip will include two UltraSparc-III cores and various other microarchitecture improvements.

Yen told us in September that the 0.13 micron process would allow the initial UltraSparc-IVs to run at around the same clock speed as the fastest UltraSparc-IIIs available when they begin shipping, and also said that while the UltraSparc-III architecture still had some room for clock speed enhancements, a dual-core UltraSparc-IV in many ways obviated the need to chase clock speeds higher and higher.

This would seem to indicate that Sun might push the clock on the UltraSparc-IIIs to maybe 1.4GHz or 1.5GHz if the 0.13 micron process allows for machines that do not need dual cores, but for the big jobs Sun would rely on the dual-core UltraSparc-IVs. Our rough estimates suggest that a dual-core UltraSparc-IV processor running at even the entry 1.2GHz speed will increase the effective processing capacity of the Sun Fire line by about 2.5 times compared to single core UltraSparc-III running at 900MHz. It's clear why Sun would need to do this. And with HP preparing dual-core PA-RISC and dual-processor modules, the reason why Sun was suddenly so open about its processor plans at the end of September becomes clear, too.

The HP PA-8800 chip, also known by its code-name "Mako," will be used in HP's Unix server and workstation lines. It has two complete PA-8700 cores, with their integrated L1 caches, an integrated L2 cache controller on a single chip and an off chip set of L2 cache SRAMs; all of this is packaged in a single module.

Each PA-8700 core on the PA-8800 chip has a 750KB data cache and a 750KB instruction cache, yielding a total of 1.5MB of L1 cache. This is the size of the cache used in the PA-8600 processors, which had a 1.5MB unified L1 data/instruction cache; the PA-8700 had a 2.25MB unified cache.

With the PA-8800s, HP seems to be breaking the data and instruction caches for each core and also shrinking them somewhat. All told, the PA-8800 will have 3MB of L1 cache, which is still a lot of memory space for a processor. The PA-8800 will also have 32MB of L2 cache, which is being supplied by Enhanced Memory Systems, which is comprised of four SRAM chips that have 10GB/sec of bandwidth.

The PA-8800 processor also includes an on-chip bus interface, similar to that in the IBM Power4 chip. The PA-8800 has a 128-bit, double-pumped 200MHz bus interface. This chip will, at 300 million transistors, be the biggest one created by any vendor to date, thanks to those large L1 caches. IBM's Power4, by comparison, has 170 million transistors.

But the switch to 0.13 micron technology will nonetheless allow HP to crank the clock to 1GHz. Sources at HP have said that the goal is to crank the clock speed of the PA-8800 up above 1GHz, if it can get away with it. The PA-8800 will plug into machines that currently support the single-core PA-8700 and PA-8700+ chips.

HP seems to be taking a similar approach with the dual-processor Itanium modules. According to John Miller, director of enterprise server marketing at HP, the company is working with Intel to launch dual-processor Itanium modules based on a variant of the "Madison" Itanium chip for shipments in the first half of 2004. Later in 2004, a dual-processor module based on the "Montecito" variant of Itanium will be available, which is shortly after the real Montecito chips are expected to be delivered.

Intel is expected to debut real dual-core Itanium chips with its "Chivano" Itaniums, due sometime in 2005. Chivano chips are effectively two McKinley cores on a single chip, and they will follow "Madison" and "Montecito" single-core Itaniums that come out in mid-2003 and mid-2004, respectively.

Some people have been saying that they believe Montecito Itaniums might be delivered as dual-core processors, and this seemed reasonable a few months ago given that Sun and HP would all have dual-core chips in the works for delivery in 2003 and IBM already has them available. But if HP and Intel are making dual-processor modules using Madison and Montecito at the time, this is probably what these people were hearing.

The question now is whether or not the fruits of HP's and Intel's labors on making dual-processor modules that can double the number of processors supported in HP's Unix, Windows, and Linux servers is a technology that other companies will want to copy. The approach that HP has taken may or may not be compatible with other server designs. And even if it is, HP says it doesn't want to share. Still, if HP can talk Intel into doing something, then IBM or Dell might be able to do it, too.

Perhaps equally significantly, whatever technologies were developed to package two processors in a single package that plugs into a single CPU slot could be deployed on Pentium 4 or Pentium 4 Xeon processors, too. This could be a great way to extend the life of current servers - something that budget-conscious IT executives in a down economy are always keen on. It will be interesting to see what happens.

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