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ComputerWire: IT Industry Intelligence

A couple of weeks ago, we divulged some of the details on the upcoming "Mako" PA-8800 RISC processor from Hewlett Packard Co for its HP 9000 and rp Series of Unix servers,

Timothy Prickett Morgan writes

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In that discussion, we speculated that HP might have to announce a new set of server chassis to accommodate the PA-8800 chips, which are essentially dual-core implementation of the current PA-8700 processor. This turns out to not be the case, which is good news for both HP and its Unix server customers.

The current crop of Unix machines from HP have supported the PA-8600 and PA-8700 generations of processors, and it is usually unlikely for server vendors to support more than two chip generations in a single set of server chassis.

Usually, the server backplane, memory subsystems, and I/O subsystems are updated with every other chip generation, since every other generation usually also includes substantial changes in the processors at the heart of a server. But usually is not always, and in the case of the rp7410, rp8400, and Superdome servers from HP, which comprise its core midrange and enterprise Unix servers, these machines will span three chip generations because HP's engineers have cleverly thought ahead. Sources at the company confirm that these three servers will support the forthcoming PA-8800 chip, which is expected to come to market sometime in 2003.

Because of this, HP's rp7410 (an eight-way machine), rp8400 (16-way) and Superdome (64-way) customers will be able to double the number of processors in their existing machines when the PA-8800 debuts. And because the PA-8800 is expected to have a clock speed in excess of 1GHz, compared to the 875MHz PA-8700+ processors that were just announced for the Superdome servers at the end of June, customers should be able to more than double the amount of work these machines can do without changing the underlying chassis.

The Mako chip includes two complete PA-8700 cores, their integrated L1 caches, an integrated L2 cache controller on a single chip and an off chip set of L2 cache SRAMs that are packaged in a single module. Each PA-8700 core on the PA-8800 chip has a 750KB data cache and a 750KB instruction cache, yielding a total of 1.5MB of L1 cache. With the PA-8800s, HP seems to be breaking the data and instruction caches for each core and also shrinking them somewhat. All told, the PA-8800 will have 3MB of L1 cache, which is still a lot of memory space for a processor. The PA-8800 will also have 32MB of L2 cache, which is being supplied by Enhanced Memory Systems, which is comprised of four SRAM chips that have 10GB/sec of bandwidth.

The PA-8800 processor also includes an on-chip bus interface, similar to that in the IBM Power4 chip. The PA-8800 has a 128-bit, double-pumped 200MHz bus interface. This chip will, at 300 million transistors, be the biggest one created by any vendor to date, thanks to those large L1 caches.

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HP readying dual-core PA-8800

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