HP readying dual-core PA-8800

Hewlett Packard Co may be Intel Corp's biggest cheerleader when it comes to the Itanium processors, particularly after its recent acquisition of Compaq Computer Corp, but that does not mean that the company is taking its foot off the pedal on the venerable PA-RISC line of processors.

On the contrary, HP has just started shipping an 875MHz version of its PA-8700 processor, called the PA-8700+, and is readying the PA-8800 processor, code-named "Mako," to offer its RISC/Unix customers substantially more processing power than the PA-8700+ chips or the "McKinley" Itanium 2 processors will offer.

The initial PA-8800 apparently uses similar copper/SOI processes and multichip module (MCM) packaging technologies to that IBM Corp is using in its Power4 "Spinnaker" line of RISC processors. The Power4 processors contain two whole Power cores and a shared 1.5MB L1/L2 cache and is effectively a two-way SMP server on a chip. HP, which uses IBM Microelectronics as its foundry, is using a similar approach with the PA-8800s. However, while IBM is using its 0.18 micron copper/SOI process for the Power4s, the foundry arm of Big Blue is using the 0.13 micron copper/SOI/low-k dielectric process for the PA-8800s. Odds are, IBM will use this same chip making process later this year when it debuts the Power4-II processors, which are supposed to run at between 1.5GHz and 1.8GHz.

The HP Mako chip includes two complete PA-8700 cores, their integrated L1 caches, an integrated L2 cache controller on a single chip and an off chip set of L2 cache SRAMs that are packaged in a single module. Each PA-8700 core on the PA-8800 chip has a 750KB data cache and a 750KB instruction cache, yielding a total of 1.5MB of L1 cache.

This is the size of the cache used in the PA-8600 processors, which had a 1.5MB unified L1 data/instruction cache. The PA-8700 had a 2.25MB unified cache. With the PA-8800s, HP seems to be breaking the data and instruction caches for each core and also shrinking them somewhat. All told, the PA-8800 will have 3MB of L1 cache, which is still a lot of memory space for a processor. The PA-8800 will also have 32MB of L2 cache, which is being supplied by Enhanced Memory Systems, which is comprised of four SRAM chips that have 10GB/sec of bandwidth. The PA-8800 processor also includes an on-chip bus interface, similar to that in the IBM Power4 chip. The PA-8800 has a 128-bit, double-pumped 200MHz bus interface.

This chip will, at 300 million transistors, be the biggest one created by any vendor to date, thanks to those large L1 caches. IBM's Power4, by comparison, has 170 million transistors. But the switch to 0.13 micron technology will nonetheless allow HP to crank the clock to 1GHz. Sources at HP say that the company has the goal of cranking the clock speed up above 1GHz, if it can get away with it.

What isn't clear is if the PA-8800's packaging is pin-compatible with the PA-8700s. If HP has managed to accomplish this, it would be great for its HP 9000 and rp Series Unix server and workstation customers, since they could more than double their processing power by swapping from PA-8700 to PA-8800 chips.

This seems unlikely, however. When HP says, for instance that it will boost the scalability of Superdome to support 128-way processing, it probably means that it is launching a revamped Superdome chassis that accommodates 64 of the PA-8800 processors. The initial Superdomes, which debuted in September 2000, supported both the PA-8600s and PA-8700s, and server chassis rarely support more than two chip generations. The odds favor a new set of boxes with the PA-8800s, which are also Itanium-ready, from HP sometime next year.

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