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Intel caches up ahead of McKinley launch

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ComputerWire: IT Industry Intelligence

Intel has pulled a little more tarpaulin off its McKinley processor, revealing ramped up cache and a faster system bus, which it claims will help to double the Itanium platform's performance,

Joe Fay writes

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The architectural changes, unveiled at the International Solid State Circuits Conference last weekend, will be built upon in further generations of the processor, as the vendor widens its assault on the high end computing market.

In the upcoming versions of the vendor's 64 bit processor, level 3 cache is shifted onto the die itself. The McKinley will feature 3Mb of Level 3 cache, along with 256K of level 2 cache and 32K of level 1 cache. This compares to 4MB of onboard level 3 cache, 96K of level 2 cache and 32K of level one cache in the first generation Itanium.

At the same time, the system bus in McKinley will be 128 bits wide, offering 6.4GB/s and running at 400MHz. This compares to its predecessor which offered 2.1GB/s, was 64 bits wide and ran at 266MHz.

Intel claims that together with an increase in clock speed to 1GHz from 800MHz on the original Itanium, the changes will help increase performance by one and a half to two times, without the need to recompile software. Optimizing applications could eke a little more performance the firm said.

The performance increase is perhaps the least you could expect from such a monster of a chip. The total size of the chip will be 421 square millimeters, and it will carry 221 million transistors, including the on-die level 3 cache.

The previous generation carried 25 million, although the off-die cache accounted for a further 300 million. Other changes include a reduction in the number of pipeline stages from 10 to eight. Two further execution units have been added.

While the Itanium is reckoned to be the biggest microprocessor ever designed, some relief is on the horizon. McKinley will be built on the same 0.18 micron process its predecessor was manufactured on.

However, Madison, the generation due after McKinley, will be built on 0.13 micron technology, potentially freeing up real estate. However, much of this will be accounted for by the 6MB of cache Madison will carry. The vendor is also planning a dual processor version Itanium, although this is not expected till the architecture moves onto a 0.09 micron process.

All these changes will be directed towards pushing Itanium into high end computing applications traditionally dominated by RISC-based architectures. At a briefing last week, Intel chief technology officer Pat Gelsinger, when asked if there was a plan for Itanium on the desktop, said "it ends up on the desktop in workstation. In terms of general desktops, no."

While the design of McKinley is now pretty much set in stone, and samples have been with customers since last year, the company still has one or two surprises to spring on the market - Gelsinger said the firm had yet to specifically say how the chip will be named.

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