AMD buys 200mm wafers for Hammer
What does that say about chip volumes?
AMD has ordered shedloads of 200mm silicon-on-insulator wafers on which it's to produce 0.13 micron 64-bit Hammer processors (next year).
The "multi million-dollar" deal was announced by wafer supplier Soitec.
The press release is tedious enough, but does it give any insight into how many Hammers AMD will bash out?
AMD claimed last week at its analyst conference that Hammer's die size is 104mm². Using basic maths, the area of a 200mm wafer is 31415.9mm². Now, chips are oblong and wafers are round, so there's bound to be some wastage, but - since we can't be arsed to mess around with differential calculus to determine a precise maximum - we'd roughly say AMD will get no more than 302 chips off a single wafer. By contrast, the company will get no more than 243 129mm² Palominos off the same wafer.
How many working chips AMD gets out of that 490 remains to be seen, but given that the company will be effectively piloting its 0.13 micron process on two generations of Athlon - Thoroughbred and, later, Barton - it should have a more mature process by the time it starts pumping out Hammer in volume late next year. And since Barton will be produced using silicon-on-insulator, AMD will get plenty of practice with that technology too.
Since Soitec hasn't said how much its wafers cost, or how many AMD is buying, we can't really make a stab at estimating full volumes. AMD could be buying from other, more tight-lipped wafer suppliers too.
In any case, Yields are difficult to guess, but having such a high number of chips per die - if AMD's 104mm² prediction proves accurate (this may just be the core, minus however much L2 cache AMD adds) - should ensure plenty of chips make it to market. ®