Sun peppers low-end with McKinley-killer Jalapeno

New buses, Gooless SMP debut

MPF You wait ages for a new bus, then two come along at once.

That was one of the surprises as Sun took the wraps off one of the year's most eagerly anticipated new chips, the Jalapeno processor, that we first told you about back in June.

Jalapeno or UltraSPARC IIIi, is the SPARC family's Celeron, if you like: a low cost UltraSPARC III derivative to shore up price/performance at the low-end. But it's more of an offensive rather than a defensive play than the Celeron comparison might suggest. It's low-cost package designed to compete with Xeon and McKinley, and make the most of IBM's excellent but expensive POWER4 packaging.

Specifications are broadly in line with what we predicted in the summer.

It's built to a 0.13 micron process using copper interconnects, uses flip chip packaging, and comes with 1MB of L2 cache. It will appear in configurations clocked between 1Ghz to 1.4Ghz. We knew about the 1.4Ghz, but not the 1Ghz: as it turns out, this is a range of likely frequencies and not a definitive product statement. Jalapeno has a 14 stage pipeline, 1MB of L2 4-way associative cache, and 266Mhz DDR memory: up to 64GB of it.

The interesting bit, and what we suspected but couldn't confirm previously, is that it deploys two new interconnects: JBUS as the chip-to-chip interconnect, and Tomatillo for I/O. But as each chip has it's own memory controller, it doesn't use JBUS for memory read/write transfers.

Sun's Kevin Normoyle describes it as Goo-less SMP (as opposed to Glueless SMP, or even Clueless SMP, we guess). Tomatillo is designed to compensate for peak PCI bus saturation, and connects the JBUS to two PCI buses. Sun reckons it can handle over 500 MB/s on both buses. An interrupt from either bus can be directed to a specific CPU.

It looks very NUMA-like. Instead of the usual cache, each Jalapeno CPU has two pairs of DDR DIMMs. Sun's Kevin Normoyle said that this offers twice the peak bandwidth if the OS is optimized for use of local memory.

Another surprise is low power operation. The chip can power down to use low frequency internal clocks without affecting JBUS or DDR frequencies.

SPARC execs made much of this aspect this morning, as we all gingerly pushed sausages around our plates at a SPARC breakfast briefing for journalists at the ungodly hour of 7am today. (We'd suggested moving this briefing nearer to the time we normally have breakfast, ie 2pm, but to no avail). More details to follow: about the SPARC, rather than the sausages. ®

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