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HP's two-core Mako chip waves hello, goodbye

Last stop before Madison

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MPF Not withstanding the outcome of the SirCam merger, HP's own chip designers are pressing on heroically.

David Johnson of HP's Fort Collins lab gave a lot of new detail on Mako aka the PA-RISC 8800 at Microprocessor Forum today. Johnson said Mako will appear at 1GHz frequencies, with a performance target of between 900 and 1000 SPEC2000 int per core, and a promise of 800,000 tpm in bigger systems.

Mako marries two 8700 cores on a die, a similar approach to IBM's POWER4. But then everyone's playing this CMP game, these days.

Mako splits 1.5MB of L1 cache between separate data and instruction caches, per core. There's 32MB of off-chip L2 cache. Cores will arbitrate between themselves for L2 cache lookups.

And the processor will be fully buzzword-compliant, using SOI, low-k dialectrics and copper, and will be built to an 8 layer 0.13 micron process The Mako bus will be compatible with McKinley, promises HP.

HP is also at pains to point out that two of its three chipset labs remain with the company.

PA-RISC will get one final revision after Mako, the 8900. ®

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