Motorola to link PowerPC direct to DRAM
On-chip controllers to accelerate data access rates
Motorola is set to build a memory controller directly on board its high-end PowerPC chips in a bid to accelerate the processor's ability to keep itself pumped up with instructions and data.
The company's focus is, of course, on better tailoring PowerPC for embedded applications, in particular communications roles. However, such a move would come as a welcome boost for its key desktop customer, Apple.
With an on-die memory controller, the PowerPC can talk to memory at its own pace and not the speed set by the main system bus. Some graphics chips use the same technique to access on-card memory as quickly as possible.
"It makes a lot more sense to add high-speed memory controllers on processors," says Motorola's PowerPC products chief, Raj Handa, cited by EE Times. "Anytime you have a bus, you have to arbitrate for the bus. Rather than let it go hungry, you could feed the processor as fast as it can be fed."
To date, chip designers have focused on connecting processors to cache memory to counter the latency of the system bus. First, L2 cache was connected across its own bus - more recently it has been integrated onto the chip itself, with a third cache, the L3, connected via the original L2 bus.
There's a law of diminishing returns to L2 and L3 cache sizes, however, and there comes a point where adding more cache memory does little to improve system performance. At that point, chip designers wonder if they could do something more useful with all those spare transistors. Adding a memory controller is one option.
There are downsides, however, and that's that it ties system developers to a specific type of memory. Handa's comments to EE Times suggest that Motorola is tending toward DDR SDRAM rather than Rambus' RDRAM. Given how far DDR prices have fallen of late and the way the world's memory makers have been predicting DDR will become the mainstream next year or 2003 at the latest, that would be a good choice for Apple and its customers.
And computing applications favour cache memory since the data they process tend to be well structured, which suits the re-use of code held in L2 cache. Direct memory access is better suited to the processing of potentially randomly formatted data streams, which makes it a better technique for, say, router processors than desktop chips.
Motorola already offers PowerPC-based parts with built-in memory controllers in the shape of its PowerQuicc family of network controller chips. ®