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Intel details 16-way DDR-based i870 chipset

Itanic, Xeon to get DDR support before Pentium 4?

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Intel took the wraps off its i870 chipset this week, the part that will allow server makers to build 16-way systems based on its Xeon and Itanium processors.

It will also be the first chipset to support Intel's Infiniband architecture. And if it ships in Q4, as suggested by the company's server roadmap, it will be the first Intel chipset to support DDR SDRAM.

The chipset has been on Intel's server roadmap for some time now, but has always been discussed in terms of four- and eight-way systems. Ultimately, the company told attendees at this week's Hot Chips conference, it will develop new interfaces that will scale up to 256-CPU systems.

Given the heat that a typical Itanium pumps out, we reckon any machine containing 256 of them is going to melt as soon as you flip the power switch, but that's another story.

Back the 870, the chipset will comprise at least three parts: a switch chip, node controller (essentially the chipset's north-bridge) and the I/O hub.

The Scalability Port Switch (SPS) contains six switch ports for hooking up four processors to each other and to the I/O hub. Each switch port uses a point-to-point coherent interconnect running a packet protocol and can transfer data at 6.4GBps in each direction, for a maximum throughput of 76.8GBps.

The SPS also supports the MESI protocol to allow chips to read - a process called 'snooping' - each others' local memory. The 1MB snoop filter operates at 400MHz and can perform 266 million snoops per second. The device has its own crossbar and bypass buses to maintain cache coherency.

The Scalable Node Controller (SNC) hooks a system's processor up to main memory across two channels of DDR SDRAM. Intel claims that's what customers wanted. So much for telling them all they really ought to go for Rambus RDRAM. Each memory channel supports four slots, each capable of holding 1GB DIMMs.

Like the SPS, the SNC works with four processors, but can connect both itself and its SPS to other clusters of four processors. It has its own Flash-based firmware unit, allowing it to check its own local components.

Finally, the I/O hub connects all the CPU clusters up to the various system buses, be they PCI-X, Infiniband or legacy ports. It's primarily designed to prefetch large quantities of data to help prevent processor stalls.

Intel appears to have discussed the availability of the i870 in terms of rolling it next year alongside McKinley (aka Itanium 2) and new Xeons, based on the 0.18 micron Pentium 4 but incorporating either 512KB or 1MB of on-die L3 cache. However, on roadmaps seen by The Register, the i870 is set to ship in Q4 this year. ®

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