Chip designers vow to cool overheating Gelsinger
All it takes is a little Pat
If current Gelsinger models are obeyed by 2010, Intel's vice president of architecture may be producing enough thermals to bring microprocessor conferences to a grinding halt. And by 2015, the heat dissipation from future Gelsingers will require portable, industrial scale para-coolants to chill the hyperbolic Veep. That promises a crisis for the industry:
"No one wants to take a Gelsinger on a plane with them," said a concerned engineer at the ISSCC solid state circuits conference in San Francisco yesterday.
Well. It certainly was brave of Chipzilla's Pat Gelsinger to decide, on behalf of the rest of the microprocessor industry, that power and thermal problems create an incipient crisis for chip designers. He even trailed the "revelation" in a press conference last week. The Register wasn't invited to this, but since we're told that we ruined his Christmas we're not surprised and we ought to shut up and take this slight like men. Or maybe even be uniquely flattered.
But at the ISSCC conference - which brings three thousand of the top world's top silicon techies together to network and to brag about their cool design work - you could float a boat with the crocodile tears shed by non-x86 engineers.
Engineers have been factoring in Smaller and Cooler into their designs for a long, long time. The heat and power crisis talked up by Gelsinger, these other folk were eager to remind us, is one largely of Intel's making. And one that Intel uniquely has to deal with. For by making clock frequency a marketing determinant, and by cranking up those deep pipelines, x86 has engineered a chip architecture without a future (as it was in the early 1990s)... into one without a future.
Apple fundamentalists (stay your pens) will point out that that today's G4 PPCs run at skin temperature, without need of a fan, and do their work in a 4-stage pipeline. The P4's triumphant 19-stage pipeline - designed with even higher frequencies in mind - has been benchmarked all the way up to PIII performance. Clearly, something's gone awry in x86land.
Yesterday we caught a couple of presentations which put the boot in ever so slightly, Neither had news value - if you've got this far, you're probably au fait with Sun and IBM chip research - but in any case, but both made merry with Gelsinger's dystopian hyperbole.
It's a kind of MAJC
Sun Microsystems gave a talk about the MAJC chip - that's the odd, VLIW multiple core processor it's designed. We didn't really learn anything new -it's multiple execution units, it nabs 18W of power at 500Mhz, that I think we already knew - but much of the presentation was geared around how the design work had focussed on minimizing power use. Right down to the insulators. Clearly, MAJC could be a mobile-friendly core in the not-too-distant future although Sun sees it as an embedded infrastructure ploy.
And then, in what we thought the most stylish presentation over the two days, a representative of IBM's S/390 processor came to deliver a technical explanation of the designer work. And oh so casually. Now rechristened the ZzzzzServer 390, the processor is designed to run at around 10W, at 770MHz, although the presenter admitted that "really it's a refrigeration unit". It's built on a 0.18 micron process, effectively bundles 18 CPUs onto the die, and has built-in failover. Oh yes, the Zzzzz/390 has built in redundancy: everything's duplicated so that if a processor unit dies, the chip shunts the workload off onto another unit without the app missing a beat. The speaker put the optimal pipeline depth at 7 or 8 stages, with the proviso that your mileage may vary. Branch prediction the speaker patiently explained, is next to impossible for commercial applications, so there's not point building this hot, heavy infrastructure that quite literally misses the point. Like many other presentations, it focussed on the 'how we got there' - but how we got there involved lots of heat-minimising design decisions. Just like MAJC.
All of which dear readers, suggests that chip designers from Compaq, Sun and IBM are rather relishing the Geltsinger meltdown. All the cards are stacked in their favour. ®
The Register is well read by the best engineers in the industry. But as far as we know, no one has yet determined the Gelsinger co-efficient. At what point does the G melt-down? Perhaps when sufficient SDMI/CPRM constants are introduced?
A Vulture baseball cap goes to the smartest equation that solves this industry conundrum. Mail us, and once we've run this through our deeply-pipelined supercomputer, the first answer not to melt will be deemed the winner.