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Intel's manufacturing and packaging crunch

Twelve inchers, .13 micron et al

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While we were at the Intel Developer Forum last week, news broke that Kyocera, one of the world's major producers of ceramic substrates, had said it wanted more money from the chip giant for the parts it made for its microprocessors. Just another supply nightmare for Chipzilla. But Intel faces more challenges than that, as Sunlin Chou, VP and general manager of its technology and manufacturing group, made clear when he talked to a small gaggle of international journalists before the forum started. His job is a particularly tough one. He said that Intel wanted to diversify into other areas and, of course, they include the lucrative Flash memory area as well as its other, networking, silicon business. Earlier, Pat Gelsinger, a senior VP in the corporation, had explained to us that Intel wanted to blanket the world with its silicon. Chou said that Intel already had four fabs in full production of .18 micron silicon, and the fifth was, in his words, "coming on line right now". That .18 micron silicon was "ramping very fast" he said. Gelsinger had earlier claimed that any shortages in this type of technology would come to an end by the end of Q1. One of the challenges Intel faces, said Chou, is that ceramic fabrication is at such high temperatures that copper interconnect at .13 micron, which the company has vowed to introduce at the end of 2001 is not suitable for this process. Flip chip packaging, which Intel wants to replace its current Slot 1 technology, is "very thin, very light and has very high performance," he said. It is also very cost-effective. Intel currently produces its chip dies on eight inch (200mm) wafer, and will do so through 2001. But, in 2002, it aims to move to twelve inch (300mm) wafers, initially in Oregon. This latter method helps reduce cost but the move to both copper interconnect technology and to 12-inchers, poses formidable challenges for the corporation. Albert Yu, a senior VP at Intel, proudly waved a 12-incher at the assembled masses last week as proof that the corporation was serious about the move. However, Intel has a policy of mirroring its fabrication plants. It is moving to .18 micron technology, aims to produce its Willamette 1.4GHz processors which also use .18 micron technology in the second half of this year, but is also committed to moving to .13 micron process using copper and then to 12-inch wafers. These moves are not trivial, and will force Intel to re-equip and/or to build additional fabrication plants, so incurring a large amount of capital investment and R&D. Said Chou: "We are on track for copper. Beyond .13 micron we can see other challenges coming along." Those could include, eventually, technology at the 30 nanometer level. Here, Chou was alluding to Moore's Law, which many estimate will come to an end in around 10 year's time. "Some people have said 'slow down' so we don't bump into this brick wall in the next 10 years," he said. "Our view is completely different. We've got a decade to do this and our industry should take this as a call for action." But Intel's short term challenges of shifting its production to faster and more economic models are probably of more concern to Sunlin Chou. Its ability to shift its entire fabrication efforts in around 18 months is a more immediate headache for Intel. ® Intel Developer Forum Q1 2000

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