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Motorola to demo 780MHz PowerPC G4+

Outlines participation at February's International Solid-state Circuits conference

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Motorola is set to discuss its second-generation PowerPC G4 line next February at the IEEE International Solid-state Circuits conference, to be held in San Francisco. The chip, the PowerPC G4+, was announced last month at Microprocessor Forum, and is the product of a major attempt by Motorola to catch up with the x86 world's lead in megaHertz. The PowerPC family has always been rather faster than x86 chips of equivalent clock speed, but of late x86 frequencies have shot so far ahead of PowerPC's that the Motorola chip has ended up looking decidedly underpowered. Whether Motorola will demonstrate the chip in action remains to be seen. However, the PowerPC design team members presenting their paper at the ISC conference will detail its operation at up to 780MHz. That's disappointing. When the chip was first discussed, Motorola said it would operate at around 700MHz but "with plenty of headroom for where we want to go", meaning scope for much higher clock speeds. The extra 80MHz doesn't seem that much headroom, frankly. Still, there's some way to go before the chip ships -- the current G4 was discussed at last year's ISC conference, and shipped in August -- so Motorola may well get the clock speed up a little higher. That will be essential given AMD and Intel are already shipping 700MHz-plus CPUs, with 800MHz and up coming next year. Still, getting PowerPC to within spitting distance of that, given the chip's inherent architectural superiorities, is clearly a very positive move. The abstract for Motorola's ISC paper offers little more information about the G4+ than we knew already -- its dual (instruction and data) 32K L1 caches, 256K on-die L2 and support for up to 2MB of backside L3 cache were revealed at Microprocessor Forum. However, we do now know that the chip will be rather bigger than the current G4, hitting 105mm squared, up from 82mm squared. So despite a move to a smaller 0.18 micron fabrication process, Motorola is cramming in a lot more transistors onto the die, primarily to accommodate the L2 cache and the chip's three extra AltiVec vector processing engines. It will also sport two extra integer units. ® Related Stories Motorola pledges fix for G4 supply problems this quarter Apple hit by 'PowerPC G4 can't reach 500MHz' bug

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