Magic Quadrant for Enterprise Backup/Recovery

Space is, of course, the final frontier. The place where you can boldly split infinitives where infinitives have never been boldly split before. We're not sure how we missed Tera, a chip fabbed up by Taiwanese outfit TSMC. But a reader has pointed us to an interesting Nasa document here which discusses how the company's microprocessor copes with parallelisation. And, incidentally, how the Tera chip fares against offerings from both Alpha and SGI. Compaq introduced its EV8 at the Microprocessor Forum a couple of weeks back but its future design, on the face of it, doesn't seem a patch on Tera's offering. (See Alpha: the chip that time forgot). Tera has taped out a chip which supports 128 thread contexts, which boiled down means that threads can be interleaved against memory wait states, thus keeping the throughput going. The company finished taping out its CMOS design at the end of July and is being fabbed up by TSMC as we write. The 64-bit design, on the face of it, beats any other similar processor that's around, and makes us wonder how the clunky Merced-Itanium will ever be anything more than a very big keyring indeed. But, we suppose, that's the triumph of marchitecture over architecture. ®

Magic Quadrant for Enterprise Backup/Recovery