Motorola speeds PowerPC to compete on clock speed
Apple clearly losing the MHz marketing battle
Motorola's pitch at Microprocessor Forum centred not the recently roadmapped chip it's now calling the G5 but on a new, intermediate version of the PowerPC 7400 (aka G4) designed to help both Motorola and Apple play catch up with the Wintel world's increasingly way higher clock speeds. Shortly after last autumn's Forum, which hosted the first public announcement of the G4, it emerged that Motorola's next chip would contain multiple G4 cores. However, that chip, codenamed V'Ger, has now become the G5, and the next processor Motorola will offer will instead be a new G4 part that's more about getting improving raw performance through higher clock speeds than clever parallel processing techniques. PowerPC processors have traditionally been faster than IA-32 chips of the same clock speed, but such has been Intel's push for higher and higher clock speeds that the PowerPC has become very clearly outpaced. And with so many buyers focusing on clock speed as the be-all and end-all of PC performance, that's left Motorola and Apple with a real marketing problem on their hands. Intel's latest Pentium III, codenamed Coppermine, will ship later this month at 700MHz, allowing it to catch up with AMD's Athlon. And this is in the same timeframe as a 500MHz G4. To date, the PowerPC's clock speed has been limited by the size of its processing pipeline. The current G4 has a four-stage pipeline -- the path of an instruction through the chip -- and that's not enough to keep a 700MHz CPU fed with instructions and data. Motorola could simply up the frequency, but the processor would have so much idle time that the speed advantage would be lost. The second-generation G4 increases the pipeline to seven stages, and to counter the reduction in the number of instructions a processor can handle per second inherent in long pipeline, the company has increased the number of instruction processing units in the chip. According to Naras Iyengar, one of the chip's design team leaders, the new G4 will feature two extra integer units, taking the total to four, in addition to the existing floating-point unit and four AltiVec units. The AltiVec system has been enhanced to handle two instructions simultaneously, each being automatically passed to the relevant unit according to the type of data involved. Following a clear industry trend, the new G4 brings the L2 cache into the chip itself to allow it to operate at the same speed as the core. The L1 caches remain the same size -- 32K instruction, 32K data -- while the on-die L2 will be 256K, connected to the L1 via a fast 256-bit wide datapath (up from the 7400's 64-bit path). Like AMD's K6-III chip, the new G4 will also support a third layer of cache between the CPU and the main memory bank, in backside configuration. It will support up to 2MB of this L3 cache. The architecture will support up to 64GB of main memory thanks to a new 36-bit addressing mode. Full details of production chips based on the new architecture will be revealed next year -- right now, Motorola's staying silent on when the second-generation G4 will ship, but given the example of the original G4, we would expect so see product this time next year. Whenever they ship, the chips will be fabbed on a 0.13 micron process, and run at 1.5V for a typical power consumption of 10W. So how much faster will the 'G4-II' be? Iyengar's put the chip at 700MHz and up, with "significant headroom for where we want to go". Room for improvement will be essential -- with Intel at 700MHz now, Motorola is going to have to come up with something higher to compete with whatever Chipzilla has on offer when the new G4 finally ships -- particularly if it's going to satisfy Apple. ®
Sponsored: RAID: End of an era?