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IBM all out for bandwidth with 170m-transistor Power4

Still keeping quiet about speed, though

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IBM did indeed put some flesh on the bones of its Power4 processor, codename Gigaprocessor, but the revelations focused solely on the upcoming chip's architecture rather than less technical but more prosaic information like, well, host fast the damn thing will be. Speaking at Microprocessor Forum, Big Blue's Power4 design chief, Jim Kahle, did reveal that the chip will contain a two processor cores plus a shared on-die L2 cache and control circuitry for an external L3 cache. Bandwidth is clearly all in IBM's eyes, and Kahle reeled off a stack of statistics such as the die-L3 line has a data throughput rate of over 40GBps, while the core-L2 line can handle over 100GBps. Each Power4 contains a chip-to-chip communications module to enhance multi-processing systems, and these modules operate at over 35GBps. The point here is that the chip and its architecture have been designed from the ground up with server roles in mind -- as Power development head Charles Moore said when he introduced the chip at last year's Microprocessor Forum -- and servers are primarily about moving information from one place to another and that, in turn is primarily about bandwidth, especially in Internet roles where usage tends to fluctuate rapidly, with frequent high bandwidth demand peaks followed by periods of relatively low usage. As Kahle put it: "Our design philosophy has been to get the right data to the right place at the right time." Kahle didn't state how fast the Power4 will actually run, beyond a broad 'greater than 1GHz', something everyone could pretty much guess from the chip's codename. However, he did confirm that the beast contains over 170 million transistors -- much of it devoted to the on-die L2 cache -- to the accompaniment of awed whistles from the Microprocessor Forum audience. According to Kahle, Power4 will sample early next year, with systems based on the processor shipping Q1 2001. IBM will offer Power4 on four-chip modules, effectively providing eight-way multi-processing through a single approximately 10cm x 10cm unit. ®

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