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AMD unveils server-oriented Athlon ‘Xeon’

Multi-processing Athlon to be first to support x86-64, AMD's 'Merced mauler'

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AMD followed yesterday's launch of the 700MHz Athlon with the announcement today that it wants to push the chip into the more lucrative server and workstation markets. And in a bid to take Intel's own new server and workstation processor, Itanium (aka Merced) head on, the Chipzilla wannabe launched it's own move into 64-bit computing: x86-64, a 64-bit extension to the AMD's existing 32-bit instruction set architecture (ISA). The move into the server and workstation worlds is clearly part of AMD's attempt to be perceived as something more than an x86 knock-off merchant. The success it has had with its 3D Now! technology and Athlon itself have helped here, but getting into more 'serious' markets should, the company hopes, prove once and for all that it's not about chasing marketshare in the low-end PC market. More pragmatically, AMD will continue to suffer badly from Intel's aggressive pricing policies while it stays in the mainstream desktop market -- moving up beyond the even the performance PC sector would go a long way to stemming all that red ink AMD is haemorrhaging. It's approach essentially boils down to an 'Athlon Xeon' part. The modified Athlon will offer better support for multi-processor systems, expanded L2 cache support -- up to 8MB of it -- and a faster, 266MHz front-side bus. How much faster than the current Athlon the new chip will be remains to be seen. The faster FSB will clearly help, but most of the chip's anticipated (by AMD) near doubling of the current 700MHz part's performance depends entirely on "projected" compiler improvements, so we'll have to wait and see. Central to Athlon's extended multi-processor role will be what AMD is calling the Lightning Data Transport (LDT), which was designed to provide a single, unified connection mechanism linking processor and North Bridge to multiple bus technologies -- PCI, System I/O (the combination of the NG I/O and Future I/O initiatives), etc. -- but neatly also serves as a multi-processor communication channel. AMD will offer the new Athlon in a dual-CPU module which connects both processors to the North Bridge chipset (via an Alpha EV6 bus) and from thence to the AGP graphics card and the system DRAM. Plug four of these together and -- bingo -- you have an eight-way MP system. LDT is a point-to-point interconnect providing a throughput of up to 6.4GBps each way and a channel width of 8, 16 or 32 bits. The 'Athlon Xeon' and LDT should ship sometime in 2000, the company said. Later, AMD will introduce its x86-64 ISA which will involve a further modification of the processor -- assuming it's not being held back for K8, of course -- that is essentially a 64-bit version of its current x86 implementation but allows the processor to behave as a 32-bit chip, when it's running existing 32-bit apps. x84-64 will also sport some additional "specialised operations" to the x86 set and add what AMD calls "technical floating point instructions", which appear extend 3D Now! to something closer to Motorola's AltiVec technology than Intel's SSE. With the 64-bit chip, AMD is clearly anticipating Intel pushing Itanium closer to the mainstream market than Intel is currently claiming. AMD's pitch is that x86-64 will offer all the benefits of 64-bit computing without having to work with a completely new ISA or limiting the performance of legacy applications. AMD VP of engineering at the company's Computation Products Group, Fred Weber, reckons solid IA-32 support will be key since almost all applications other than operating systems and databases will never be 64-bit. True, but since Intel too now seems to realise this and has upgraded its Itanium IA-32 support accordingly, AMD's lead here may not prove so solid. However, AMD is also promising multiple x86-64 cores on a single chip, which is something it could possibly do well before Intel gets any multi-core Itanium processors out of the door. ®

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