IBM will flesh out its next generation Power4 line of PowerPC processors at the Microprocessor Forum in San Jose later today. Power4, which IBM first started talking about as Gigaprocessor at last year's Forum, is aimed for 2001 (won't it be busy then, friends?), will have 170 million plus transistors and will consist of two chips. It will, as reported here earlier, run at 1.1GHz and deliver 11,000 MIPS at launch, when it will be fabbed in 0.18 micron. IBM however intends to shift it to the dream combination of 0.13 micron, copper and silicon-on-insulator (SOI) by 2002-3, which is expected to kick clock speeds up in the direction of 2GHz. That alone should be enough to make Power4 a monster, but IBM argues that its design, which places a great deal of emphasis on the routing of data within the CPU and on smart caching, is inherently more efficient. Power4 will execute up to five instructions with each clock cycle. ®