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IBM 1GHz 64-bit PPC to deliver 11,000 MIPS

Ultra SMP the way to go, says Big Blue

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More information is leaking out about the next generation IBM PowerPC Power4, the 64-bit chip line formerly known as Gigaprocessor, and due next year at clock speeds of over 1GHz. The first chips will be sub-0.18 micron, with 200 million transistors or more. Power4 will have two microprocessors on a single piece of silicon, and at 1.1GHz should be able to deliver 11,000 MIPS. The architecture comes out of Austin, and chips will be fabbed at the Fishkill Semiconductor Center. With microprocessor performance still increasing much faster than memory hierarchy performance, DRAM latency will grow and bus speed will not keep pace with increases in microprocessor speed. Likewise, circuit density will continue to increase faster than circuit speed. To leverage the circuit density increase, faster uniprocessors with superscalar designs or VLIW and derivatives such as EPIC (explicitly parallel instruction computing, favoured by Intel) are needed. More systems functions and multiple processors on a chip (SMP, co-processors and redundant processors for error detection and fault tolerance) seems to be IBM's preferred route. Whatever the architecture or design, processors spend most of their time waiting for cache misses, so the optimised feeding of processors is the main performance challenge. Software design trends such as OOP and JIT compilation will increase the memory hierarchy load, so the design challenge is to deal with the memory hierarchy bandwidth. IBM says it believes that its approach to parallelism (Ultra SMP) is superior to Intel's EPIC since EPIC increases the demand for memory hierarchy bandwidth and low latency. IBM also claims that EPIC is less suitable for JIT Java compilation as it needs lengthy compilation and a large optimisation window. Another difficulty that IBM identifies with EPIC is in future binary compatibility, resulting in a probable need to recompile. Could it be that a JavaOS will rise again? Explicit parallelism -- Ultra SMP -- is IBM's answer, which it claims exploits existing parallelism in code (and particularly SMP-enabled server applications with multiple threads). The approach allows multiple threads per chip with multiple physical processors, or multiple logical processors with hardware thread switching. Above all, the memory hierarchy would be used more efficiently, IBM says, with less bandwidth for each useful instruction, as well as less cache latency. As a consequence, IBM will preserve PowerPC and S/390 binary compatibility, and optimise for SMP and cluster performance with multiple RISC "cores" per chip, while Intel creates a new IA-64 instruction set architecture and optimises uniprocessor performance. IBM won't have the fastest uniprocessor, but it should do a better job of preserving the software investment. Intel is left with some sticky problems, such as software migration; performance issues with the new architecture; x86 compatibility mode performance; and SMP performance. These puddings aren't yet ready for eating -- and there are other chefs too -- so we'll just have to wait and see which proves tastier. ®

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