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IBM to debut ‘Gigaprocessor’ CPU at Hot Chips

Power4 chip to be first multi-core part in PowerPC family

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Internet Security Threat Report 2014

IBM will next week unveil its latest Power CPU, the chip line that formed the basis for the PowerPC family. The Power4 processor will beat Motorola to the goal of unveiling a multi-core PowerPC chip. According to EE Times, Power4 will contain two cores and an L2 cache on a single die constructed using a 0.18 micron process and copper interconnect technology. The chip is scheduled to be unveiled at a paper given at the Hot Chips conference next week. Members of the chip's development team said the chip will support a bus speed of greater than 500MHz, and while they would not confirm the chip's clock speed, they did say their goal was a bus speed half the frequency of the clock speed, clearly implying CPU speeds of 1GHz or more. That suggests that the Power4 is the so-called 'Gigaprocessor' outlined by the project's head, Charles Moore, at the Microprocessor Forum last October. When quizzed about the difference between a server-oriented CPU and a more general microprocessor, Moore pointed to the former's high level of reliability, extended multi-processing capability, very high I/O bandwidth and focus on minimising memory latency -- the imbalance in speed between processor, system bus and RAM. According to the latest reports, the Power4 is designed to support 32-way MP systems, using 16 of the dual-core chips. The processor is due to ship in 2001, which may well put it behind Motorola's multi-core version of the PowerPC G4, codenamed v'ger, which is due late 2000. That said, it looks likely IBM will unveil its chip before Motorola, which has yet to officially release the initial, single-core iteration of the G4. That launch is due to take place "sometime in the third quarter", according to Motorola PowerPC marketing manager Will Swearingen. ®

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