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Motorola preps enhanced PowerPC G3

Faster, smaller G3 to match IBM's fast silicon on insulator based PPCs

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Internet Security Threat Report 2014

Even as Motorola is -- we hope -- gearing up for its launch of the PowerPC 7400, aka G4, the company appears to be continuing to evolve the current G3 line. According to anonymous sources cited by Apple-oriented Web site MacOS Rumors, the G3, officially known, in its two versions, as the PowerPC 740 and 750 (the 740 is the release that's pin-compatible with the old PPC 603/604 chips), will be updated as the PowerPC 745 and 755, respectively. Codenamed Goldfinger, the upgrades will take the chips' clock speeds to 500MHz and beyond. Bus multiplier support will be raised from the current 8x to 10x and above. The source claimed the new chips would be manufacturered at a 0.22 process, but since the current top-speed G3 chips are already produced at that spec., we suspect the new ones could be shrunk to 0.20 micron, the same as the upcoming G4, using copper interconnect technology. IBM is already preparing speed-hiked PPC 750s based on its silicon on insulator (SOI) technology, so clearly Motorola feels the need give its own version of the chip a boost, and while Motorola is concentrating on the G4, making the rumoured upgrades to the G3 line is perfectly plausible. Initially shipping at 0.2 micron, IBM's SOI G3 will rapidly move down the micron scale to 0.18 and, later, 0.13, according to earlier reports. The 0.18 micron SOI-based PPC is likely to be the next iteration of the G4, however, one that will take the processor's clock speed beyond 600MHz. If the G4 debuts, as Motorola has pledged, before October, the second release could happen as soon as early to mid-2000. Towards the end of next year, Motorola has roadmapped the release of the next major G4 upgrade, codenamed 'V'ger', which integrates four PPC 7400 cores on a single chip. It is now believed that V'ger will also integrate 256KB of L2 cache on the die and support up to 8MB of L3 cache in a backside configuration. The L1 caches will be increased from the G3 and early G4's 32KB data/32KB instruction configuration to 64KB each. ®

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