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IBM reveals high-speed chip packaging

Improves performance of Web servers, apparently

IBM yesterday unveiled a new processor packaging system designed to make CPU-to-system data throughput more efficient. Aimed initially at high performance networking systems, IBM's High Performance Chip Carrier (HPCC) encases the processor in a fluoropolymer dielectric material. The result, claimed the company, is a faster electrical current between the chip and the rest of the system. Essentially, HPCC appears to reduce electrical noise between chip and bus, much as IBM's Silicon on Insulator technology reduces it within the processor itself. IBM said it designed the technology for chip speeds "in the gigahertz range", which should hit the market next year, initially in high-performance servers, in particular Web servers, which IBM claimed would see clear improvements in performance. Certainly server processors are the target of IBM's PowerPC development, much of which centres on its upcoming 'Gigaprocessor' chip. ®

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