How Cyrix sees bus architecture
Outlines the problems and opportunities
Chip manufacturer Cyrix has posted an interesting presentation it made at the WinHEC conference at the beginning of the month. Thanks to JC for pointing us to the PDF file here. The presentation contains clear diagrams which show the layout of typical frontside and traditional "backside" (ahem) architecture. It also points to the problems involved in implementing level one and level two caches on microprocessors and contrasted integrated level two cache with external cache. If you read between the lines, you will detect some future technology Cyrix will integrate. ®
Sponsored: RAID: End of an era?