Hard facts emerge about Willamette
Architecture details show 1Mb L2 cache on die
Intel's eagerly anticipated Willamette IA-32 technology is taking shape as hard details have emerged from highly authoritative sources. Few details from Intel have been available, although at the Intel Developer Forum in Palm Springs in February, senior VP Paul Otellini said the technology was on time and was a completely new IA-32 architecture. Our source, based at Intel Germany, claimed that Willamette could have as many as 450 pins in its socket design, use dual channel Rambus memory and employ a chipset called Tehama. She said that K7 floating point (FP) numbers we posted last week were "disappointing" and that Willamette architecture would have no problems if its FP was as low as we reported. Willamette, as well as Merced, have existed as design concepts for seven years so far, she added. "They called Merced P7 then and Willamette P68," she said. She said: "Look for much larger level one ROP (RISC-like) storing 'trace' aches in Willamette. Coppermine and its derivatives will likely be the last of the P6 line." There could be as much as 128K level one data cache on Willamette processors, it has emerged. According to our source, who wishes to remain anonymous for obvious reasons, the cache and the core of Willamette architecture are totally different from P6 technology. The L2 cache, which is likely to be 1Mb, is broken into hundreds of squares, suggesting a massively parallel schema, she claimed. Intel architects have dedicated a lot of space to decoding instructions in Willamette. ®
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