What the Hell is…Camino and Rambus all about?
Number one in an occasional series for those who can’t be bothered to RTFM
Those awfully clever folks at Intel have managed to bump up processor power by around 200 times since the introduction of the 486 ten years ago. Trouble is, memory technology has only improved by a measly 20 times in the same period. Fancy caches can help a bit, but something fundamental needs to change in order to get the most system bang for your CPU buck. DRAM vendors have increased memory densities by almost 1,000 fold – that’s faster than even Microsoft’s bloatware demands – and this means that fewer memory devices are needed to reach the RAM requirements of a system, allowing new ways of enabling the CPU and memory to talk to each other to be investigated. Rambus aims to deliver more than ten times the performance of today’s memory subsystems while keeping costs down and providing a means of reusing SDRAM DIMMs. Intel’s delayed Camino (820) chipset will feature a gizmo called a Memory Translator Hub (MTH) enabling either (but not both) SDRAM DIMMs or direct RDRAM SRIMMs to be used. An 820-based system will support up to 1.5Gb of SRIMM memory or 1Gb if DIMMs are used. Camino is based on a hub architecture with a Memory Controller Hub (MCH) at its heart. The MCH in turn talks to the CPU through the host bus (at 133MHz), the graphics subsystem through the AGP bus (AGP 4X) and the memory through Rambus. Everything else is handled by the I/O Controller Hub (ICH) which has a direct link to the MCH. Clear? It gets more complex. 300MHz Rambus direct RDRAM is only supported at 100MHz FSB speeds, while 400MHz parts are happy at 133MHz too. Could this be the reason Camino is late? Who can tell? So what about the performance benefits then? Rambus will enable the CPU and memory subsystem to communicate at up to 800MHz and 1.6 Gb/second while using around a fifth of the power – that’s around three times the bandwidth of today’s conventional 100MHz SDRAM. And in the future, the ability of the MCH to talk to up to four memory channels simultaneously will bring bandwidths up to 6.4Gb/second in high-end systems. Unlike today’s memory, you’ll need to fit continuity modules in empty memory slots because Rambus daisy chains its memory a bit like SCSI devices. While this may at first sound a tad clunky, it apparently means that clocking the memory is simpler and is claimed to be electrically superior, offering active power management of individual memory modules. Find out more at Rambus ®
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