Our mole over at the Intel Job Centre has provided us with a fresh wish list for Merced engineers. Readers will recall that "The Sixth Vulture" provided us with a stream of vacancies for Merced engineers only a week or two back. Now, he says, a spate of further vacancies is up for grabs. The latest job ads are for 28 in the last few days with some subtle changes from the last batch of vacancies. Some are re-posted vacancies but one, available at Redmond, has now moved to Satan Clara, Chipzilla Central. Although the word "Merced" does not appear as often as it did a week ago, there is a little McKinley teaser. We quote from one ad: "Exciting developments are being made on the Merced microprocessor to be released in mid-1999. And as we look into the future, McKinley, the second-generation 64-bit architecture, will run at a minimum of 1GHz and will feature the largest on-chip Level 2 cache of any Intel chip. More importantly, the McKinley architecture will support a memory large enough to fit almost all databases, resulting in high-speed queries and other executions." A job for a Logic Engineer at Satan Clara is also interesting: "In this position, you will be responsible for developing functional tests for IA64 CPU manufacturing. You will work closely with the IA64 CPU team for developing strategies and setting up tools for functional pattern generation through design simulator. "Pattern generation methodology must cover all platforms which can source tests for developing manufacturing screens to achieve targeted DPM goals. You will also work closely with Product Engineers responsible for converting the design simulation outputs to test vectors, who will demand a very detailed knowledge of the RTL model of the Front Side BUS and its external protocols. You will also have responsibility for defining methodology and writing necessary codes for generating self contained test patterns and for initial debug of functional pattern failures on the production tester." And this one is intriguing because it mentions the "latest" Merced processor. "I/O TIMING DESIGN ENGINEER In this position, you will be responsible for validating next generation latest Merced(tm) CPU and future IA-64(tm) bit-architecture microprocessor, and front side bus on various systems topologies. You will be responsible for various aspects including bus timing generation; simulating bus performance under various motherboard and package topologies; validating and improving the I/O design, and generating SPICE models to be used by OEMs." When we asked an Intel representative about what the phrase "latest Merced" meant, he told us that the advertising agency had made a mistake. ® Related Stories Merced project in utter disarray Intel steps up Merced recruitment drive Intel goes hell for leather to hire Merced staff Compaq Merced designers flee coop