IA-64 Architecture Innovations

Merced Track 2

This is a presentation jointly given by John Crawford, Architect & Intel Fellow at Intel, and Jerry Huck, leading architect at Hewlett Packard at the Intel Developer Forum. Because it is a long presentation, each of the files IA64-1.JPG to IA64-18.JPG contains three slides each. You can see photographs of the Merced package here, while our full coverage of the Intel Developer Forum is is here. These are the titles of each slide: 1. IA-64 Architecture Innovations 2. Agenda 3. Traditional architectures: limited parallelism File One 4. IA-64: explicit parallelism 5. IA-64: principles 6. Predication File Two 7. Predication review 8. Introducing parallel compares 9. Eight Queens example File Three 10. Eight Queens example 11. Eight Queens example 12. Five predicate compare types File Four 13. Predication benefits 14. Speculation review 15. Hoisting uses File Five 16. Introducing the NaT -- "not a thing" 17. Propagation 18. Exception deferral: more than skin deep File Six 19. Control speculation summary 20. Store barrier 21. Introducing data speculation File Seven 22. Data speculation: uses can be hoisted 23. Advanced load address table: ALAT 24. Architectural support for data speculation File Eight 25. Speculation benefits 26. Agenda 27. Branch instruction File Ninee 28. Branch predicates 29. Compare and branch in same cycle 30. Multi-way branch File Ten 31. Software pipelining 32. Basic loop example 33. Loop support: unrolling File Eleven 34. Software register re-naming 35. Software register re-naming 36. Software register re-naming File Twelve 37. Software register re-naming 38. Software register re-naming 39. Introducing rotating registers File Thirteen 40. Introducing rotating registers 41. Introducing rotating registers 42. Introducing rotating registers File Fourteen 43. Introducing rotating registers 44. Loop support: rotating registers 45. Introducing rotating predicate registers File Fifteen 46. Introducing rotating predicate registers 47. Introducing rotating predicate registers 48. Introducing rotating predicate registers File Sixteen 49. Introducing rotating predicate registers 50. Introducing rotating predicate registers. File Seventeen More on rotating predicate registers File Eighteen ®

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