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NatSemi Cyrix licenses Rambus for Jalapeno

x86 core's performance so dependent on memory speed Rambus deal essential

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National Semiconductor's Cyrix subsidiary yesterday said it had licensed Rambus' Direct DRAM memory interface, and that it planned to support the technology in upcoming system-on-a-chip products. Cyrix executive VP Jean-Louis Bories said the decision to license Rambus memory technology was prompted by the bandwidth requirements of the company's high-speed x86-compatible CPUs. "As our integrated processors approach speeds of 1GHz, high memory bandwidth and low latency become ever more critical to achieving the optimum balance of performance and cost," he said. The technology will be added to Cyrix's forthcoming 600MHz-and-up M3 chip based on the Jalapeno x86 core, the speed of which is known to be highly dependent on memory performance because its design increases processing speed by handling instructions in sequence rather than running them in parallel. Today's announcement came as no big surprise. Last year, Jalapeno project manager Greg Grohoski told The Register that Jalapeno and the M3's on-chip memory manager would both require the speed and bandwidth only Rambus could offer (see Cyrix, IDT, Rise ready low-end PC processors). The Jalapeno-based M3 is due to sample in Q4 -- standalone Jalapeno chips should become available next year. ®

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