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Intel leaks details of Foster, Merced, McKinley

Four FPUs in Merced and a whole lot more

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An Intel presentation on the future of its IA-32 and IA-64 technology has revealed mechanical details of how its Merced processor will be implemented. And the document, available for download from an Intel FTP site, reveals other, hitherto unknown details of its implementation, as well as information about Foster and McKinley. Clive Turvey first discovered the URL. The presentation is compiled by Stephen Smith, corporate VP of Intel's microprocessor products group, based at Intel's HQ in Santa Clara. Merced is still on target for release in the middle half of next year using 0.18 micron process technology. McKinley will be released in 2001, while Madison, an IA-64 performance part, and Deerfield, an IA-64 price/performance part, follow soon after, using a 0.13 micron process. Its new IA-32 architecture will provide large on-chip L1 and L2 cache and give bus bandwidth of 3.2Gbps, with L1 cache performing at 32Gbps and L2 cache at 8Gbps. The Merced will have two extended precision FMACs, two SP FMACs and provide executioon of up to eight SP FLOPs per cycle. That, claims Intel, will give 20 times the performance of the Pentium Pro and three times the performance of Tanner on 3D graphics. Merced will provide "complete" IA-32 binary compatibility, according to the presentation. The Merced will manage memory latency with a three-level cache hierarchy. That will include separate instructions and data L0 caches, a larger, unified L1 cache on the die, and the L2, which is off the die, will provide large overall capacity. Bus and memory utilisation will provide better deferred transaction support, with cache line size optimised to conserve bandwidth. The dedicated full speed L2 bus will free the system bus for multiprocessing, with increased page size of up to 256MB. Its error handing includes extensive ECC coverage on processor and bus, with hardware support for correcting single bit ECC errors. According to Intel, the microarchitecture definition of Merced is now complete. The company is in the final stages of functional RTL validation and is booting the OS kernel. The cartridge for Merced includes heat dissipation technology on top of the die, a "cost effective" performance substrate, Intel-designed static cache RAM, a full speed cache bus and separate signal and power connections for signal integrity. Intel and the industry is currently shipping 64-bit SDKs and pre-silicon software development tools. The compiler optimisation is meeting its milestones, with ISVs currently porting their server and workstation applications. Merced is already booting IA-64 operating systems, with chipsets and system designs on track for the first samples. Those OSes include HP/UX, Solaris, SCO, SGI Irix, D/UX (Tru64), Novell Modesto and Win64. Intel's target for McKinley is to create clock speeds of over 1GHz, with very large, high-speed on-chip caches. The bus is a superset of the Merced bus with three times the bus bandwidth, with target production for late 2001. Future IA-64 proliferations will use 0.13 technology. ®

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