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Intel EPIC roadmap attempts to unite IA-32 and PA-RISC

Another leaked Intel doc might create a stink

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Internet Security Threat Report 2014

An Intel downloadable document has revealed more about its EPIC 64-bit architecture than most of us would want to know. The document, written by Intel fellow John Crawford and HP lead architect Jerry Huck, goes into massive detail about the future shape of software to come. Currently, according to the presentation, mispredictions limit performance and small blocks restrict code scheduling freedom. Then follows an argument about so-called "big endian" and "little endian" architecture -- one which the 64-bit Alpha architecture seems to circumvent. "Branching is a barrier," proclaims the joint presentation, and load delays are compounded by machine widths. The explicit parallelism that HP and Intel talkabout will make it explicit in machine code, rather than in software. Here, Intel and HP talk about their "Three Es" -- Expose, Enhance and Exploit. Both IA-32 and PA-RISC will use EPIC technology, according to the leaked presentation. According to HP and Intel, explicit parallelism will break through the CISC and RISC argument, by destroying sequential execution. EPIC will use one basic block and the new compiler will give a larger scheduling scope, with predication in nearly all instructions. Half of all branches will be removed, according to Intel and HP. Both companies use a classic chess board scene to show that they have the answer to solving the Big Endian-Little Endian problem. In their view, "speculation" takes up nine cycles with three potential mispredicts, while "predication" takes up seven cycles with only one potential misdirect. The document is on Intel's ftp download site. ®

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