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IEEE conference programme shows seepage

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Major chip manufacturers are set to unveil new microprocessors at a conference in the US in mid-February. The agenda of the IEEE Solid State conference, lists presentations from executives from IBM, AMD, Intel and HP, and accidentally discloses details of chips they have in the offing. According to the programme HP will show a 64b PA RISC chip using a .25 micron process, together with 1Mb of level one cache data and 0.5Mb level on instruction caches. The processor will run at 500MHz on a 21.3 x 22mm square die. IBM Micro will be showing a G5 chip for the S/390 platform, using a .15 micron chip running at 600MHz and running at 500MHz in a 10+2 shared environment. AMD will show its K7 at .25 microns and describes its out of order FPU, which it claims will execute FPU instructions at two FLOPS per cycle, 3DNow! SIMD instructions at four FLOPS per cycle peak rate and up to three MMX SIMD instructions per cycle. Intel is demonstrating a 600MHz IA-32 chip, according to the agenda. ®

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