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Microsoft leaks Merced details

So much for detente...

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An unholy row is set to break out between Intel and Microsoft after the software company revealed details of the up-and-coming Merced architecture. According to reports in the newsgroup COMP.ARCH, Microsoft has "accidentally" issued some binaries on CDs they have sent to their ISVs. One of the pieces of code, dubbed IAS, IA-64(TM) architecture (EAS 2.3) Assembler Rewrite X8 Apr 28 1998, which does not run because of missing DLLs, does however dump error messages and lists of assembler mnemonics and strings relating to asserts. Those include, for example: EM_DECODER_ROTATING_SIZE_LARGER_STACK_FRAME: Size of rotating region is larger than the stack frame, suggesting Merced will use rotating registers with variable sizes -- codenamed Trimaran. And another dump shows: "EM_DECODER_WRITE_TO_ZERO_REGISTER: Destination general register r0 is invalid, showing that Intel has not abandoned its plans for special zero registers on the chip. Another dump shows: EM_DECODER_ODD_EVEN_DESTS: Both destination floating-point registers have odd or even values. According to postings in the newsgroup, this suggests either instructions with two results or bundle restrictions. ®

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