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AMD, Intel locked in bus marketing war

Celeron with 100MHz frontside bus next year?

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Intel is likely to introduce a Celeron processor with a 100MHz bus next year but will wait until Katmai is released to differentiate these processors from its low end chips, it has emerged. But the possibility of a 100MHz Celeron is likely to confuse end users, already bewildered by a plethora of clock speeds, different chip flavours and branding campaigns. Yesterday, AMD claimed it had an edge on Intel's technology because it would have a frontside bus of 200MHz on its forthcoming K7. (Story: K7 architecture to stay slottish) However, end users and others should beware because AMD and Intel are not comparing apples with apples, warned senior Dataquest UK analyst Joe D'Elia. He said: "The front side bus tends to be where the DRAM is concentrated. Yes, Intel will do a 133MHz front side bus, unfortunately they will not connect DRAM to it. Next year, the chipsets will support Direct Rambus with a direct connection to the processor at 800MHz and that is independent of the front side bus." D'Elia said: "The K7 bus is totally different -- it doesn't have a bus in the same way -- it has a point to point bus, so everything connected to it has its own access." Chip companies should not use front side bus speeds as a marketing device, he said. "If they do so, they're not comparing apples with apples". He said: "Mendocino is the same core as Deschutes so it can run at 100MHz but whether Intel decides to do so is purely a marketing decision. Intel has to differentiate the Celeron from the Pentium II. If they can get it to run at the same bus speed, people would ask why should they buy Pentium IIs." D'Elia said: "When Katmai comes out with the 820 chipset, it will work with Direct Rambus later next year and then Intel can differentiate it from the Celeron. At that point, Intel could release a Celeron with a 100MHz bus." But the slot architecture is unlikely to disappear for Intel processors, said D'Elia. He said that the slot architecture was necessary for processors at the high end because it gave greater flexibility, particularly at the high end. "Xeons do need the ability to have different cache sizes," he said. "High end machines couldn't do it on a single die using present technology and it would be too expensive anyway. Nor can you put the cache on the motherboard because you would have performance degradations." An Intel representative said: "The Pentium II will never be socketed." Roadmaps showed slot architecture up to the end of next year at least. He confirmed it was feasible to create Celerons with 100MHz frontside buses but said no decision had yet been made about whether Intel would release one. As already revealed here, Intel will release a 366MHz Celeron in early January, a 433MHz Celeron in February and a 466MHz Celeron after that. ®

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