Transmeta reveals radical new chip design
The company is planning a 'philosophers stone' chip that will run x86 apps faster, without cloning x86 chips
Chip design operation Transmeta has finally tipped its hand by filing a patent application for a radical new product which could conceivably run virtually any application faster than the original. If the company is barking up the right tree, it will be able to build a completely new line of processors which will be able to run all existing Intel software, without Transmeta having had to maim its own hardware in order to do so. The patent application doesn't exactly tell you this from the title though, which is: "A memory controller for a microprocessor for detecting a failure of speculation on the physical nature of a component being addressed." Clear? Thought not. The application actually covers a range of 21 interrelated claims, the gist of which seems to be that Transmeta thinks it can design a cheap, fast processor which uses a range of cute techniques to overcome the shortcomings of cloning and emulation. The techniques are applicable to all kinds of target hardware, operating systems and applications, but obviously x86 and Wintel apps are the most important ones that have to be tackled. They allow for the design of a new, original processor (VLIW seems to be the preference, but this doesn't have to be the case) which can run x86 and other applications faster than the original. The point of the "memory controller" aspect of the application is to allow for the detection of the difference between memory and memory-mapped I/O. Emulation systems such as SoftPC have to deal with situations where the hardware used by the application being run is different, or maybe isn't even there. Instructions to I/O also have to be executed in a particular order, so dealing with this, if you don't know which is memory and which memory-mapped I/O, slows down emulators massively. Transmeta intends to combine microprocessor and memory controller into something it refers to as a "morph host." The CPU will include code morphing software and a hardware morph portion. How this works is as follows: The target application gives target instructions to the code morphing software for translation into host instructions, which the morph host can then execute. At the same time, the target OS receives calls from the target application and transfers these to the code morphing software. Says the application: "In a preferred embodiment of the microprocessor the morph host is a VLIW processor designed with a plurality of processing channels." The VLIW processor itself can be much simpler, faster and cheaper than current processors, because it "does not include circuitry to detect issue dependencies or to reorder, optimise and reschedule primitive instructions. This, in turn, allows faster processing at higher clock rates than is possible with either the processors for which the target application programs were originally designed or other processors using emulation programs to run target application programs. However, the processor is not limited to VLIW processors and may function as well with any type of processor such as a Risc processor." So although Transmeta isn't yet telling us much about the particular processor it will be building, it's showing us how that processor could be entirely new, and yet can avoid being marginalised by the x86 compatibility issue. In fact it seems likely that Transmeta's product will be intended to take advantage of Intel's switch over to 64-bit over the next five years. Transmeta needn't just provide the mechanism to run legacy apps better than IA-32 - its techniques could allow it to do this better than IA-64. There are various cute aspects to Transmeta's approach. The code morphing software includes a translator portion "which decodes the instructions of the target application, converts those target instructions to the primitive host instructions capable of execution by the morph host, optimises the operations required by the target instructions, renders and schedules the primitive instructions into VLIW instructions (a translation) for the morph host, and executes the host VLIW instructions." Translations don't necessarily have to be done over and over again, because there's a "translation buffer" (which is currently specced at two megabytes) which stores common translations, and these can be reused. There's also a little bit of interception to deal with self-modifying code, where the original of a stored translation might have changed, rendering the translation inaccurate. There are "target registers" in the hardware that hold the state of the registers of the target processor the app thinks it's running on. So the hardware will be keeping far better track of the state the emulated hardware is supposed to be in, and can emulations faster, because it doesn't have to keep stopping to check what's going on. Transmeta gives an example which would have 64 working registers in the integer unit and 32 in the floating point unit. The company sums the patent application up as being for "a memory controller for a microprocessor including apparatus to both detect a failure of speculation on the nature of the memory being addressed, and apparatus to recover from such failures." It sounds dull, but basically it means the hardware can run a lot faster because it can (usually) tell what it's doing better, and in cases where it finds it can't, then it can get out of the situation without a fatal error. ®
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