Second-stage PowerPC G4 details emerge
Motorola to offer multi-core CPU at 1GHz early 2000
Tantalising details have emerged of Motorola's plans for the forthcoming PowerPC G4 processor. According to information received by Apple-oriented Web site MacOS Rumors, the first G4 CPU, codenamed 'Max', is designed to push the transition between old, G3-based hardware and new systems designed specifically for G4. Max will be made available in 300-500MHz clock speeds, utilise 0.18-micron copper wiring technology, contain two 32K on-chip L1 caches and support up to 2MB of backside L2 cache. A 1.8V processor core will offer reduced power consumption. The chip will also provide a new 128-bit 'MaxBus' bus technology, which allows CPUs to communicate directly with each other in multiprocessor systems. However, older 64-bit '60x' buses will also be supported. Max will be 30-50 per cent faster than the PowerPC 750, and will ship with Motorola's AltiVec vector processing extensions for greater performance gains in graphics and multimedia applications. It is scheduled to ship in volume by the middle of next year. Beyond Max lies 'V'Ger' (named after an alien entity in the first Star Trek film, trivia fans). Initially running at 500MHz, Motorola has it mapped out to 800MHz and beyond to 1GHz. V'Ger will contain multiple Max cores, all of which can be switched on and off, on the fly, according to performance and power consumption requirements. 0.15-micron supports higher clock speeds while keeping power comsumption down, and further performance is gained from an on-chip L2 cache. The chip will support up to 8MB of external L3 cache, but it's unclear how much difference this will really make unless the on-chip L2 is actually quite small. V'Ger should ship late 1999, early 2000. ®
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