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Cyrix, IDT/Centaur, Rise ready low-end PC processors

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Pretenders to Intel's low-end crown Cyrix, IDT/Centaur and Rise all announced next generation Basic PC-oriented x86-compatible processors at the Microprocessor Forum in San Jose, California today. Cyrix's product is M3, the first chip based on its new Jalapeno x86 core. According to project manager Greg Grohoski, the design focus was on increasing the bandwidth of the host PC's memory bus, rather than attempt to allow ever more program instructions to be processed simultaneously, the approach taken by Intel and by AMD for K7. Jalapeno is designed for high-speed, 600MHz and up processing. M3 adds to that a built-in memory manager, 256K of on-chip L2 cache and an "advanced" 3D graphics engine. It also supports MMX and AMD's 3DNow instruction set extensions. However, the memory manager, while improving data throughput, requires RAMBUS' RDRAM memory technology. RDRAM may be faster than SDRAM, but it's also more expensive -- in addition to the cost of the chips, RAMBUS levies a 2-5 per cent royalty -- which could limit the number of M3 supporters. That said, M3 is not due to become available until Q4 1999 -- and then only as samples -- giving RAMBUS time to get its technology established. Rise Technology's mP6 family is set to ship sooner, sampling this quarter and going into full production not long after. The company claims the chip offers 15 per cent better core CPU performance than the Pentium II for a given clock speed. And it can execute three MMX instructions per cycle, faster than any other x86 processor. At the same time, Ken Munson, principal engineer on the mP6, said it had a very low power consumption -- unused CPU circuitry is turned off automatically -- making it ideal for notebooks. Munson would not, however, be drawn on the speeds the chip would be available in, nor would be comment on pricing. The initial chip will offer just 16K of L1 cache, as will the next release, the mP6 II, which is designed to compete with the Mendocino version of Intel's Celeron, currently performance hamstrung by the Great Stan's keenness that it not compete with PII. Like M3, mP6 will feature 256K on-chip L2 cache. That's not a feature shared by IDT/Centaur's WinChip 4, however. Instead, according to Centaur president Glen Henry, the chip will simply boast a much larger L1 cache. "There's a 1-2 per cent difference in performance between a mix of L1 and L2 on-chip cache and just L1, but a 50mm increase in die size," he said. Since Centaur's design philosophy is all about keeping the die size down -- and therefore reducing the cost of each chip -- it opted for just L1. Henry admitted previous WinChips were "lagging in megahertz", something version 4 was to address. The new release will offer speeds of 400-500MHz and contain 128K of L1 cache. It also uses a new core that is designed to reduce the likelihood of data not being found in the cache thus forcing the CPU to wait for it to arrive via the system bus. Version 1 of WinChip 4 will go into production in the second half of next year, said Henry, using 0.25-micron technology. A faster (500-700MHz) release based on the 0.18-micron process, will begin production in the first half of 2000. All three vendors' chips will use Socket 7 interfaces. "We won't do Slot 1," said Henry. "It's not where our market is." "There's still plenty of demand out there for Socket 7," added Grohosk. ® Click for more stories

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